As is known in the art, selecting an input/output (I/O) buffer requires that the designer consider board topologies, board, response-time characteristics (i.e., speed, rise time, overshot, etc.), bus cross-talk, etc. Unfortunately, this cannot be done until the actual board has been manufactured. Selecting the optimal I/O buffer has many advantages such as optimized signal quality, lower switching noise and lower power consumption. More particularly, because designs are becoming faster, and power consumption is becoming a concern for the current and future platforms, each signal transmission has to be specifically designed and every watt saved. Integrated circuit (IC) I/O buffers determine the quality of the signal as well as consume roughly 30–40% of the total IC power. Hence, careful selection of the optimal I/O buffers might have a great impact on the final signal quality and total power consumption by potentially recommending an optimal drive buffer. Selecting high current drive buffers would result in better rise time at the expense of higher switching noise. Selecting the optimal buffer drive for a given board topology would eliminate any unnecessary switching noise on the board, resulting in better signal quality and reliability.
Any given Field Programmable Gate Array (FPGA) device, being programmable, enables the designer to “tweak” the I/O buffers to optimize its performance. However, in many cases, an Application Specific Integrated Circuit (ASIC) device follows the FPGA design, which does not enable the I/O buffers therein to be “tweaked”, therefore requiring a pre-selected set of I/O buffers.